1. Field of Invention
The present invention relates to a signal transmission circuit, a CMOS semiconductor device, and a circuit board, and more particularly, to a signal transmission circuit having an assist-circuit, a CMOS semiconductor device having an assist-circuit, and a circuit board having an assist-circuit.
2. Description of Related Art
As the size of a semiconductor integrated circuit device increases, the size of a semiconductor chip that forms the semiconductor integrated circuit device is also increased. As a result, the length of a signal wire that is formed inside the semiconductor chip (for example, a signal wire for distributing a clock, a signal wire that forms a bus line, or the like) tends to be long.
FIG. 1 shows the configuration of each type of signal wire formed inside an integrated circuit device. A large-scale integrated circuit device is formed inside a square semiconductor chip CP whose side length is approximately 15 mm through 20 mm. Therefore, it is not unusual that the wire length of a signal wire LIN formed inside an integrated circuit device reaches over 20 mm.
A shown in FIG. 1 shows a wiring configuration of a circuit in which the line length of a signal line LIN between a driver circuit DR and a driven circuit RC is less than 100 xcexcm. B shows a wiring configuration of a circuit in which the line length exceeds 20 mm. C shows a wiring configuration of a circuit like a bus line or a clock distribution line in which multiple driven circuits RC are connected to a signal line LIN.
Wiring capacitance CL is generated on a signal line LIN that connects between a driver circuit DR and a driven circuit RC. Input capacitance CG is formed at the input terminal of the driven circuit RC. The values of the wiring capacitance CL in A, B, and C differ from each other, and the values of the input capacitance CG in A, B, and C differ from each other. The value of the input capacitance CG is proportional to the number of driven circuits RC connected to the signal line LIN. The value of the wiring capacitance CL is proportional to the length of the signal line LIN.
Seeing the wiring configurations A, B, and C from this view point, the wiring configuration A, when it is connected to the signal line LIN, has the smallest capacitance value. Subsequently, the capacitance value of the wiring configuration B is larger than that of the wiring configuration A, and the capacitance value of the wiring configuration C is larger than that of the wiring configuration B. Depending on the value of this capacitance, the transmission characteristic of a signal differs greatly.
FIG. 3 shows the wave-forms of step response waves that are generated when a step pulse is supplied to each of these wiring configurations A, B, and C. FIG. 3A shows the waveform of a step response wave that is generated by the wiring configuration A shown in FIG. 1. FIG. 3B shows the wave-form of a step response wave that is generated by the wiring configuration B shown in FIG. 1. FIG. 3C shows the wave-form of a step response wave that is generated by the wiring configuration C shown in FIG. 1. As is evident from FIG. 3, at the wire length of the wiring configuration A shown in FIG. 1, virtually no delay is visible in the rise of the step wave-form. However, in the wiring configurations B and C, the shapes of the step waves are greatly rounded, generating long response delays. In particular, this tendency appears prominently in the wiring configuration C having a long signal line LIN to which many driven circuits RC are connected.
FIG. 4 shows the wave-forms of response waves. The wiring configuration A transmits an input pulse to the driven circuit RC almost normally. However, the wiring configurations B and C hardly transmit the pulse to their driven circuits RC, respectively. In other words, it can be seen that a signal line having a large capacitive cannot transmit a pulse having a narrow pulse width. This is a main factor inhibiting development of a large-scale semiconductor chip.
The content of this factor also applies as a similar phenomenon to a signal line that connects between integrated circuit devices packaged on a circuit board (printed wiring board).
It should be noted that, in order to increase the degree of integration of a semiconductor integrated circuit device, the processing dimensions of a device such as a transistor need to be fined, and the widths of the wires must be formed thin. In this respect, it can be considered that the value of the capacitance generated on the signal line will become small. However, when the wire width is formed thin, the thickness of the insulation layer is also formed thin at the same time. Consequently, the wiring capacitance CL of the signal line and the input capacitance CG of the driven circuit RC do not decrease by a large amount even if the formation area is decreased as a result of the increased degree of integration.
On the other hand, in order to solve this problem, for example, in a circuit in which a clock pulse is distributed to many circuit regions MAP as shown in FIG. 5, a large capacitance driver circuit DR1, a medium capacitance driver circuit DR2, and a small capacitance driver circuit DR3 can be connected to the circuit, which is seemingly a feasible method. However, if driver circuits DR1, DR2, and DR3 are connected to each signal line LIN, the number of circuits inside the integrated circuit increases. As a result, the amount of power consumption also increases. In addition, the number of circuits for a signal to pass through also increases. Therefore, the timing accuracy also deteriorates.
It is an object of the present invention to propose a signal transmission circuit that is capable of assuring a signal transmission even through a long signal line without increasing the degree of integration inside an integrated circuit.
It is also an object of the present invention to provide a signal transmission circuit, a CMOS semiconductor device, and a circuit board that are capable of solving the above-stated problems. The object of the present invention can be achieved by a combination of characteristics described in the independent claims of the present invention. The dependent claims of the present invention determine further advantageous embodiments of the present invention. This invention proposes a signal transmission circuit having a configuration in which an assist-circuit, which has a low output impedance and outputs the mid point voltage of a power source voltage, is connected to a position on a signal line of the signal transmission circuit.
According to a signal transmission circuit based on this invention, an assist-circuit, which has a low output impedance and outputs the midpoint voltage of the power source voltage, is connected to a position on a signal line having a large wiring capacitance or a large input capacitance. As a result, the voltage of the signal line is driven centered at the mid point voltage of the power source voltage. In other words, the driven circuit is driven centered at its own threshold voltage.
Since the output impedance of the assist-circuit is low, the amplitude of the signal is kept small. However, since the driven circuit is driven centered at its own threshold value, the driven circuit is turned on and off assuredly, and is able to receive the signal even if the amplitude of the given signal is small. Moreover, since the output impedance of the assist-circuit is low, the time constant (in this case, it is the product of the resistance and capacitance) that determines the transition time of the transmission signal becomes small. As a result, the signal can be passed through the signal transmission circuit at a high speed.
Therefore, an input pulse can be transmitted through a signal line without distorting the wave-form of the input pulse even if the sum of the wiring capacitance and input capacitance is large.
Moreover, since the amplitude of the transmission signal becomes small, the amount of transitional charge-discharge currents that are supplied to the wiring capacitance and input capacitance are reduced. As a result, the amount of power consumed during an operation is also reduced.
In order to solve the above-stated problems, according to the first aspect of the present invention, a signal transmission circuit having a driver circuit for sending out a transmission signal, a signal line for propagating the transmission signal, and a driven circuit, which is driven by two power source voltages VSS and VDD (VDD greater than VSS), for taking in the transmission signal that is propagated through the signal line is provided. This signal transmission circuit has an assist-circuit for outputting a prescribed voltage, which is larger than the power source voltage VSS and smaller than the power source voltage VDD, to the signal line.
According to the second aspect of the present invention, a signal transmission circuit as described in the first aspect of the present invention is provided such that the driven circuit has a digital circuit which outputs one of two values of a binary output voltage in response to a voltage input to the driven circuit, and the assist-circuit outputs a voltage that approximately matches a threshold voltage at which an output of the digital circuit is inverted from one of the two values of the binary output voltage to the other of the two values of the binary output voltage.
According to the third aspect of the present invention, a signal transmission circuit as described in the second aspect of the present invention is provided such that the assist-circuit outputs a voltage that is approximately a midpoint voltage of the power source voltages VSS and VDD.
According to the fourth aspect of the present invention, a signal transmission circuit as described in the first aspect of the present invention is provided such that the assist-circuit has an output impedance that is lower than an output impedance of the driver circuit.
According to the fifth aspect of the present invention, a signal transmission circuit as described in the fourth aspect of the present invention is provided such that the output impedance of assist-circuit is xc2xc through xc2xd of the output impedance of the driver circuit.
According to the sixth aspect of the present invention, a signal transmission circuit as described in the first aspect of the present invention is provided such that the assist-circuit has a first inverter including an input terminal and an output terminal, and a feedback circuit in which the input terminal of the first inverter is connected with the output terminal of the first inverter.
According to the seventh aspect of the present invention, a signal transmission circuit as described in the sixth aspect of the present invention is provided such that the driven circuit has a second inverter such that a beta ratio of the second inverter is approximately equal to a beta ratio of the first inverter.
According to the eighth aspect of the present invention, a signal transmission circuit as described in the first aspect of the present invention is provided such that the assist-circuit has a P-type FET and an N-type FET such that a forward bias voltage is applied to gates of the P-type FET and N-type FET, respectively.
According to the ninth aspect of the present invention, a signal transmission circuit as described in the first aspect of the present invention is provided such that the assist-circuit has a voltage source which outputs a prescribed voltage that is larger than the power source voltage VSS and smaller than the power source voltage VDD.
According to the tenth aspect of the present invention, a signal transmission circuit as described in the ninth aspect of the present invention is provided such that the assist-circuit further has a low impedance buffer circuit which lowers an output impedance of the voltage that the voltage source has output.
According to the eleventh aspect of the present invention, a signal transmission circuit as described in any of the first through tenth aspects of the present invention is provided such that the signal transmission circuit further has a cut-off means which cuts off a current that flows between the signal line and the assist-circuit.
According to the twelfth aspect of the present invention, a signal transmission circuit as described in the first aspect of the present invention is provided such that the assist-circuit has an NAND gate and a feedback circuit in which an input terminal of the NAND gate is connected with an output terminal of the NAND gate.
According to the thirteenth aspect of the present invention, a signal transmission circuit as described in the twelfth aspect of the present invention is provided such that the NAND gate includes a control terminal to which a control signal, which cuts off a current that flows between the signal line and the assist-circuit, is input.
According to the fourteenth aspect of the present invention, a signal transmission circuit as described in the first aspect of the present invention is provided such that the assist-circuit has an NOR gate and a feedback circuit in which an input terminal of the NOR gate is connected with an output terminal of the NOR gate.
According to the fifteenth aspect of the present invention, a signal transmission circuit as described in the fourteenth aspect of the present invention is provided such that the NOR gate includes a control terminal to which a control signal, which cuts off a current that flows between the signal line and the assist-circuit, is input.
According to the sixteenth aspect of the present invention, a signal transmission circuit as described in the first aspect of the present invention is provided such that the assist-circuit is connected to a termination of the signal line.
According to the seventeenth aspect of the present invention, a CMOS semiconductor device having a signal transmission circuit that has a driver circuit for sending out a transmission signal, a signal line for propagating the transmission signal, and a driven circuit, which is driven by two power source voltages VSS and VDD(VDD greater than VSS), for taking in the transmission signal that has been transmitted through the signal line is provides such that the signal transmission circuit has an assist-circuit which outputs a prescribed voltage, which is larger than the power source voltage VSS and smaller than the power source voltage VDD, to the signal line.
According to the eighteenth aspect of the present invention, a CMOS semiconductor device as described in the seventeenth aspect of the present invention is provided such that the assist-circuit has an output impedance that is lower than an output impedance of the driver circuit.
According to the nineteenth aspect of the present invention, a CMOS semiconductor device as described in the seventeenth aspect of the present invention is provided such that the assist-circuit has a beta ratio that is approximately equal to a beta ratio of the driven circuit.
According to the 20th aspect of the present invention, a circuit board having a first semiconductor device that has a driver circuit for sending out a transmission signal, a second semiconductor device, which is driven by two power source voltages VSS and VDD (VDD greater than VSS), having a driven circuit for taking in the transmission signal, and a signal line pattern for propagating the transmission signal from the driver circuit to the driven circuit, is provided. This circuit board has an assist-circuit which outputs a prescribed voltage, which is larger than the power source voltage VSS and larger than the power source voltage VDD, to the signal line.
According to the 21st aspect of the present invention, a circuit board as described in the 20th aspect of the present invention is provided such that the assist-circuit has an output impedance that is lower than an output impedance of the driver circuit.
The outline of the above-described invention does not list all the required characteristics of the present invention. Sub-combinations of these characteristics group are also covered by the scope of the present invention.